general description the ds4125, ds4155, ds4156, ds4160, ds4311, ds4312, ds4622, and ds4776 ceramic surface-mount crystal oscillators are part of maxim? ds4-xo series crystal oscillators family. these devices offer output fre- quencies at 125mhz, 155.52mhz, 156.25mhz, 160mhz, 311.04mhz, 312.5mhz, 622.08mhz, and 77.76mhz. the clock oscillators are suited for systems with tight toler- ances because of the jitter, phase noise, and stability performance. the small package provides a format made for applications where pcb space is critical. these clock oscillators are crystal based and use a fun- damental crystal with pll technology to provide the final output frequencies. each device is offered with lvds or lvpecl output types. the output enable pin is active-high logic. these clock oscillators have very low phase jitter and phase noise. typical phase jitter is < 0.6ps rms from 12khz to 20mhz. the devices are designed to operate with a 3.3v ?% supply voltage, and are available in a 5.0mm x 3.2mm x 1.49mm, 10-pin lccc surface-mount ceramic package. applications infiniband bpon/gpon ethernet 10gbe sonet/sdh features ? < 0.6ps rms from 12khz to 20mhz jitter ? lvds or lvpecl output types ? 3.3v operating voltage ? 5.0mm x 3.2mm x 1.49mm, 10-pin lccc ceramic package ? -40? to +85? operating temperature range ? lead free/rohs compliant ds4125/ds4155/ds4156/ds4160/ds4311/ds4312/ds4622/ds4776 ds4-xo series crystal oscillators ________________________________________________________________ maxim integrated products 1 ds4125 v cc outp outn lvds option oe gnd 0.01 f 0.1 f 100 ds4125 v cc outp outn lvpecl option oe gnd 0.01 f 0.1 f 50 50 pecl_bias v cc - 2.0v typical operating circuits rev 0; 7/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration and selector guide appear at end of data sheet. + denotes a lead-free package. the lead finish is jesd97 category e4 (au over ni) and is compatible with both lead-based and lead-free soldering processes. ordering information part temp range pin-package ds4125 d+ -40 c to +85 c 10 lccc ds4125p+ -40 c to +85 c 10 lccc ds4155 d+ -40 c to +85 c 10 lccc ds4155p+ -40 c to +85 c 10 lccc ds4156 d+ -40 c to +85 c 10 lccc ds4156p+ -40 c to +85 c 10 lccc ds4160 d+ -40 c to +85 c 10 lccc ds4160p+ -40 c to +85 c 10 lccc ds4311 d+ -40 c to +85 c 10 lccc ds4311p+ -40 c to +85 c 10 lccc ds4312 d+ -40 c to +85 c 10 lccc ds4312p+ -40 c to +85 c 10 lccc ds4622 d+ -40 c to +85 c 10 lccc ds4622p+ -40 c to +85 c 10 lccc ds4776 d+ -40 c to +85 c 10 lccc ds4776p+ -40 c to +85 c 10 lccc
ds4125/ds4155/ds4156/ds4160/ds4311/ds4312/ds4622/ds4776 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power-supply voltage (v cc ) .......................................-0.3v, +4v operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range ...............................-55 c to +85 c soldering temperature profile (3 passes max of reflow).................see ipc/jedec j-std-020 specification parameter symbol conditions min typ max units operating voltage range v cc (note 1) 3.135 3.3 3.465 v i cc_d lvds, output loaded or unloaded 50 70 i cc_pu lvpecl, output unloaded 45 65 operating current i cc_pi lvpecl, output load 50 at v cc - 2.0v 70 95 ma output frequency f out f nom mhz oscillator startup time t startup (note 2) 50 ms frequency stability f total over temperature range, aging, load, supply, and initial tolerance (note 3) -50 f nom +50 ppm frequency stability over temperature with initial tolerance f temp v cc = 3.3v -35 +35 ppm initial tolerance f initial v cc = 3.3v, t a = +25 c 20 ppm frequency change due to v cc f vcc v cc = 3.3v 5% -3 +3 ppm/v frequency change due to load variation f load 10% variation in termination resistance 1 ppm aging (15 years) f aging -7 +7 ppm integrated phase rms; 12khz to 5mhz, v cc = 3.3v, t a = +25 c < 0.5 integrated phase rms; 12khz to 20mhz, v cc = 3.3v, t a = +25 c < 0.6 jitter j rms integrated phase rms; 12khz to 80mhz, v cc = 3.3v, t a = +25 c < 1.0 ps input-voltage high (oe) v ih (note 1) 0.7 x v cc v cc v input-voltage low (oe) v il (note 1) 0 0.3 x v cc v input leakage (oe) i leak gnd oe v cc -50 +5.0 a ds4-xo series crystal oscillators
ds4125/ds4155/ds4156/ds4160/ds4311/ds4312/ds4622/ds4776 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = 3.135v to 3.465v, t a = -40? to +85?, unless otherwise noted.) parameter symbol conditions min typ max units lvds output high voltage v ohlvdso 100 differential load (note 1) 1.475 v output low voltage v ollvdso 100 differential load (note 1) 0.925 v differential output voltage | v odlvdso | 100 differential load 250 425 mv output common-mode voltage variation v lvdsocom 100 differential load 150 mv change in differential magnitude or complementary inputs | v odlvdso | 100 differential load 25 mv offset output voltage v offlvdso 100 differential load (note 1) 1.125 1.275 v differential output impedance r olvdso 80 140 l vsslvdso outn or outp shorted to ground and measure the current in the shorting path 40 output current l lvdso outn or outp shorted together 6.5 ma output rise time (differential) t rlvdso 20% to 80% 175 ps output fall time (differential) t flvdso 80% to 20% 175 ps duty cycle d cycle_lvds 45 55 % propagation delay from oe going low to logical 1 at outp t pa1 200 ns propagation delay from oe going high to output active t p1a 200 ns lvpecl output high voltage v oh output connected to 50 at pecl_bias at v cc - 2.0v v cc - 1.085 v cc - 0.88 v output low voltage v ol output connected to 50 at pecl_bias at v cc - 2.0v v cc - 1.825 v cc - 1.62 v differential voltage v diff_pecl output connected to 50 at pecl_bias at v cc - 2.0v 0.595 0.710 v rise time t r-pecl 200 ps fall time t f-pecl 200 ps duty cycle d cycle_pecl 45 55 % propagation delay from oe going low to output high impedance t paz 200 ns propagation delay from oe going high to output active t pza 200 ns note 1: all voltages referenced to ground. note 2: ac parameters are guaranteed by design and not production tested. note 3: frequency stability is calculated as: f total + f initial + f temp + ( f vcc x 0.165) + f load + f aging . ds4-xo series crystal oscillators
pin description ds4125/ds4155/ds4156/ds4160/ds4311/ds4312/ds4622/ds4776 ds4-xo series crystal oscillators 4 _______________________________________________________________________________________ single-sideband phase noise at f 0 = f nom (dbc/hz) f m = 77.76mhz 125.00mhz 155.52mhz 156.25mhz 160.00mhz 311.04mhz 312.5mhz 622.08mhz 10hz -60 -70 -70 -70 -70 -65 -65 -60 100hz -95 -100 -100 -100 -100 -95 -95 -90 1khz -122 -120 -120 -120 -120 -113 -113 -107 10khz -126 -120 -120 -120 -120 -113 -113 -107 100khz -131 -125 -125 -125 -125 -118 -118 -113 1mhz -143 -142 -142 -142 -142 -137 -137 -131 10mhz -149 -149 -149 -149 -149 -149 -149 -147 20mhz -153 -153 -153 -153 -153 -153 -153 -150 pin name function 1 oe active-high output enable. has an internal pullup 100k resistor. 2, 7C10 n.c. no connection. must be floated. 3 gnd ground 4 outp positive output for lvpecl or lvds 5 outn negative output for lvpecl or lvds 6 v cc supply voltage ep exposed paddle. the exposed pad must be used for thermal relief. this pad can be connected to ground. single-sideband phase noise at f 0 = f nom
ds4125/ds4155/ds4156/ds4160/ds4311/ds4312/ds4622/ds4776 ds4-xo series crystal oscillators _______________________________________________________________________________________ 5 detailed description the devices consist of a fundamental-mode, at-cut crystal and a synthesizer ic that can synthesize any one of these frequencies: 77.76mhz, 125mhz, 155.52mhz, 156.25mhz, 160mhz, 311.04mhz, 312.5mhz, and 622.08mhz. all devices support two types of differential output dri- vers: lvds and lvpecl. when the oe signal is low, lvpecl outputs go to the pecl_bias level of v cc - 2.0v, while the lvds outputs are a logical one. see figures 2 and 3 for an lvds and lvpecl output timing diagram. additional information for more available frequencies, refer to the ds4106 data sheet at www.maxim-ic.com/ds4106 . x1 x2 tri- state phase det filter lc-vco /n outseln /m outdrv v cc gnd oe outp outn ds4125/ds4155/ ds4156/ds4160/ ds4311/ds4312/ ds4622/ds4776 figure 1. functional diagram oe outp t p1a t pa1 0.7 x v cc 0.3 x v cc outn figure 2. lvds output timing diagram when oe is enabled and disabled oe outp pecl_bias pecl_bias pecl_bias pecl_bias outn 0.7 x v cc 0.3 x v cc t paz t pza figure 3. lvpecl output timing diagram when oe is enabled and disabled
ds4125/ds4155/ds4156/ds4160/ds4311/ds4312/ds4622/ds4776 ds4-xo series crystal oscillators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. chip information substrate connected to ground process: bipolar sige theta-ja (c/w) 90 package type document no. 10 lccc 56-g5032-002 selector guide + denotes a lead-free package. the lead finish is jesd97 category e4 (au over ni) and is compatible with both lead-based and lead - free soldering processes. part frequency (nom) (mhz) frequency stability (ppm) output type top mark ds4125 d+ 125.00 50 lvds 25d ds4125p+ 125.00 50 lvpecl 25p ds4155 d+ 155.52 50 lvds 55d ds4155p+ 155.52 50 lvpecl 55p ds4156 d+ 156.25 50 lvds 56d ds4156p+ 156.25 50 lvpecl 56p ds4160 d+ 160.00 50 lvds 60d ds4160p+ 160.00 50 lvpecl 60p ds4311 d+ 311.04 50 lvds 31d ds4311p+ 311.04 50 lvpecl 31p ds4312 d+ 312.50 50 lvds 32d ds4312p+ 312.50 50 lvpecl 32p ds4622 d+ 622.08 50 lvds 62d ds4622p+ 622.08 50 lvpecl 62p ds4776 d+ 77.76 50 lvds 76d ds4776p+ 77.76 50 lvpecl 76p package information (for the latest package outline information go to www.maxim-ic.com/dallaspackinfo .) 1 2 3 6 5 4 top view oe n.c. n.c. n.c. n.c. n.c. gnd v cc outn outp + (5.00mm 3.20mm 1.49mm) ds4125 *ep *exposed pad pin configuration thermal information
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